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<title>Visium Options (Using the GNU Compiler Collection (GCC))</title>

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<h4 class="subsection" id="Visium-Options-1"><span>3.19.51 Visium Options<a class="copiable-link" href="#Visium-Options-1"> &para;</a></span></h4>
<a class="index-entry-id" id="index-Visium-options"></a>

<dl class="table">
<dt><a id="index-mdebug-2"></a><span><code class="code">-mdebug</code><a class="copiable-link" href="#index-mdebug-2"> &para;</a></span></dt>
<dd><p>A program which performs file I/O and is destined to run on an MCM target
should be linked with this option.  It causes the libraries libc.a and
libdebug.a to be linked.  The program should be run on the target under
the control of the GDB remote debugging stub.
</p>
</dd>
<dt><a id="index-msim-9"></a><span><code class="code">-msim</code><a class="copiable-link" href="#index-msim-9"> &para;</a></span></dt>
<dd><p>A program which performs file I/O and is destined to run on the simulator
should be linked with option.  This causes libraries libc.a and libsim.a to
be linked.
</p>
</dd>
<dt><a class="index-entry-id" id="index-mhard_002dfloat-10"></a>
<a id="index-mfpu-5"></a><span><code class="code">-mfpu</code><a class="copiable-link" href="#index-mfpu-5"> &para;</a></span></dt>
<dt><code class="code">-mhard-float</code></dt>
<dd><p>Generate code containing floating-point instructions.  This is the
default.
</p>
</dd>
<dt><a class="index-entry-id" id="index-msoft_002dfloat-15"></a>
<a id="index-mno_002dfpu-1"></a><span><code class="code">-mno-fpu</code><a class="copiable-link" href="#index-mno_002dfpu-1"> &para;</a></span></dt>
<dt><code class="code">-msoft-float</code></dt>
<dd><p>Generate code containing library calls for floating-point.
</p>
<p><samp class="option">-msoft-float</samp> changes the calling convention in the output file;
therefore, it is only useful if you compile <em class="emph">all</em> of a program with
this option.  In particular, you need to compile <samp class="file">libgcc.a</samp>, the
library that comes with GCC, with <samp class="option">-msoft-float</samp> in order for
this to work.
</p>
</dd>
<dt><a id="index-mcpu-13"></a><span><code class="code">-mcpu=<var class="var">cpu_type</var></code><a class="copiable-link" href="#index-mcpu-13"> &para;</a></span></dt>
<dd><p>Set the instruction set, register set, and instruction scheduling parameters
for machine type <var class="var">cpu_type</var>.  Supported values for <var class="var">cpu_type</var> are
&lsquo;<samp class="samp">mcm</samp>&rsquo;, &lsquo;<samp class="samp">gr5</samp>&rsquo; and &lsquo;<samp class="samp">gr6</samp>&rsquo;.
</p>
<p>&lsquo;<samp class="samp">mcm</samp>&rsquo; is a synonym of &lsquo;<samp class="samp">gr5</samp>&rsquo; present for backward compatibility.
</p>
<p>By default (unless configured otherwise), GCC generates code for the GR5
variant of the Visium architecture.  
</p>
<p>With <samp class="option">-mcpu=gr6</samp>, GCC generates code for the GR6 variant of the Visium
architecture.  The only difference from GR5 code is that the compiler will
generate block move instructions.
</p>
</dd>
<dt><a id="index-mtune-16"></a><span><code class="code">-mtune=<var class="var">cpu_type</var></code><a class="copiable-link" href="#index-mtune-16"> &para;</a></span></dt>
<dd><p>Set the instruction scheduling parameters for machine type <var class="var">cpu_type</var>,
but do not set the instruction set or register set that the option
<samp class="option">-mcpu=<var class="var">cpu_type</var></samp> would.
</p>
</dd>
<dt><a id="index-msv_002dmode"></a><span><code class="code">-msv-mode</code><a class="copiable-link" href="#index-msv_002dmode"> &para;</a></span></dt>
<dd><p>Generate code for the supervisor mode, where there are no restrictions on
the access to general registers.  This is the default.
</p>
</dd>
<dt><a id="index-muser_002dmode-1"></a><span><code class="code">-muser-mode</code><a class="copiable-link" href="#index-muser_002dmode-1"> &para;</a></span></dt>
<dd><p>Generate code for the user mode, where the access to some general registers
is forbidden: on the GR5, registers r24 to r31 cannot be accessed in this
mode; on the GR6, only registers r29 to r31 are affected.
</p></dd>
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